Front-End RTL Design Engineer

You will evaluate AI model outputs for RTL hardware design tasks. Your reviews will use RTL designs, hardware specifications, reference solutions, verification tests, and project guidelines.

You will explain your decisions clearly and maintain consistent quality across repeated evaluation tasks.

• Evaluate model outputs using project rubrics and document evidence-based judgments.
• Review source materials and model outputs against project guidelines.
• Explain your decisions in clear written feedback.
• Check RTL hardware design work involving ASIC and FPGA projects.

Compensation details are not provided in the listing.

• Pay: No rate or fixed project amount is provided.
• Schedule: 20+ hours per week.
• Availability: Four hours of daily overlap with Pacific Time.
• Location: Open worldwide.
• Language: Fluent in English.
• Experience: At least 3 years of front-end digital design experience on ASIC or FPGA projects, from RTL through synthesis.
• RTL skills: Fluent Verilog and SystemVerilog, including microarchitecture, datapaths, finite-state machines, pipelines, FIFOs, clock-domain crossings, and clock gating.
• Analysis: Ability to read timing and quality-of-results reports and understand which RTL or constraint changes affect area, timing, or power.

Apply on OpenTrain with your resume, then complete the application on the hiring site.

AI training is the human work behind systems that learn from examples. In this role, your engineering judgment and clear feedback help evaluate and improve AI systems working with hardware design.